As is appreciated in the art, the performance of modern complex microprocessor-based systems, such as personal computer workstations and portable computers, depends in large part on the quantity of digital data per unit time communicated among the various system components. Conventional data processing systems typically include a microprocessor as a central processing unit (CPU), connected to off-chip memory and input/output (I/O) functions via a bus. Specifically, conventional PC-architectures utilize an x86-architecture microprocessor as a CPU, and which communicates with memory and performs I/O functions via a so-called "chipset" of integrated circuit logic functions that buffer and control bus traffic between these subsystems and the CPU. In conventional systems that utilize a single CPU operating in a sequential fashion, the rate of data traffic on the bus may be optimized in a relatively straightforward manner.
However, certain improvements in system architecture require more complex bus transactions between the CPU and the memory and I/O subsystems to optimize the effects of the improvements on system performance. The use of multiple CPUs in a single system is well-known in the field of data processing systems, resulting in a so-called "multiprocessor" system. The system performance is improved, of course, by the additional CPUs executing instructions in parallel.
Another example of such an improvement is the use of "out-of-order" execution by the CPU, in which the CPU executes instructions, including memory and I/O accesses, in a sequence that is different from that specified by the controlling program. Out-of-order execution typically examines the sequence of instructions ahead of the instruction currently being executed, and selects those instructions for execution that are not dependent upon the completion of preceding instructions, saving the dependent instructions for execution at a later time when the dependency is cleared, regardless of the instruction order specified in the program. Out-of-order execution thus executes instructions based upon their "readiness" to execute, rather than strictly on program order.
According to each of these approaches, however, the maximum performance improvement may be obtained only by increasing the complexity of bus transactions. One way in which bus transactions are handled with maximum efficiency in such advanced systems is through the use of "split" transaction cycles, which are also referred to in the art as "asynchronous" bus transactions. An asynchronous bus transaction refers to a transaction in which a bus request is made in one bus cycle, and in which one or more responses to the bus request are made in later bus cycles that are not contiguous in time to the request. For example, an asynchronous bus transaction request may be made in a first bus cycle, followed by bus cycles of a different type (which may be accesses to and from a different CPU from that CPU making the request in the prior cycle), which are then followed by responses to the asynchronous bus transaction request. Of course, such split bus transactions require identifying information, through the use of address or control signals, in order for the CPU or CPUs to recognize and properly respond to the bus activity in any one of the bus cycles.
By way of further background, the bus protocol for PENTIUM microprocessors (also referred to as 586-class microprocessors) available from Intel Corporation that operate at clock rates of 75 MHz or faster, and Pentium-class microprocessors compatible therewith available from other sources, is generally referred to in the art as "P54C" bus protocol. As is known in the art, P54C Pentium-class microprocessors support dual-processor operation, and as such several signals in P54C microprocessors, such as memory/IO select M/IO#, data/control select D/C#, write/read select W/R#, address status signal ADS#, and split cycle signal SCYC, are input/output signals. However, asynchronous bus transaction cycles are not supported by P54C Pentium-class microprocessors or by the current support logic (commonly referred to as "chipsets") designed for use therewith. As such, in order to provide the functionality of asynchronous bus transactions according to conventional technology, new bus architectures beyond those heretofore provided by Pentium-class microprocessors would be necessary.
By way of further background, the "P6" or PENTIUM-PRO microprocessors available from Intel Corporation, and Pentium-Pro-class microprocessors compatible therewith available from other sources, provide support for asynchronous transactions. UK Patent Application Publication GB 2 287 161 A, published on Sep. 6, 1995, describes such support by way of a dedicated signal from a requesting bus agent to request a deferred transaction, and from a target bus agent to indicate granting of the deferral of the transaction. However, these dedicated signals are not provided in, and are thus incompatible with, the P54C bus protocol indicated hereinabove. As a result, asynchronous transactions are not presently available in computer systems implemented with the P54C bus architecture. In addition, it is believed that the P6 operates to request the asynchronous transaction with an identifier that is presented on certain of its address pins in a time-multiplexed manner relative to the address value, thus requiring multiple bus cycles to request the transaction.